Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available High Definition (HD) video formats, the computational complexity of De full search (FS) ME algorithm is prohibitively high, whereas the PSNR obtained by fast search ME algorithms is low. Therefore, ill this paper, we present Dynamically Variable Step Search (DVSS) ME algorithm for Processing high definition video formats and a dynamically reconfigurable hardware efficiently implementing DVSS algorithm. The architecture for efficiently implementing DVSS algorithm. The simulation results showed that DVSS algorithm performs very close to FS algorithm by searching much fewer search locations than FS algorithm and it outperforms successful past search ME algorithms by searching more search locations than these algorithms. The proposed hardware is implemented in VHDL and is capable, of processing high definition video formats in real time. Therefore, it can be used in consumer electronics products for video compression, frame rate up-conversion and de-interlacing(1)

Bias Temperature Instability in CMOS Digital Circuits from Planar toFinFET Nodes

Reliability of electronic circuits has become one of the most prominent grand challenge in the near-term (2013-2020) and long-term (2021-2028) technology roadmap for the semiconductor industry. The CMOS scaling trends has resulted in deeply scaled device dimensions. In addition, the slow paced scaling of supply voltages in the decananometer CMOS era, has exacerbated stress levels on semiconductor ICs. Today, atomic scale device dimensions are triggering the discretisation/quantization of the reliability effects, e.g. although a decananometer CMOS device only consists few oxide traps, each single trap excitation or emission directly impacts a device’s threshold voltage shift. As a consequence, the scale of intrinsic parameter fluctuations in modern day devices are becoming increasingly unpredictable at the system level. For example, the reliability effects are highly workload-dependent, i.e. no more averaging, where the time constants are ranging from picoseconds to days. Last but not least, the nature of CMOS/beyond-CMOS scaling (towards the edge of the matter) will introduce new stimulating challenges and fundamental barriers for reliability, i.e. lithography, process control, new materials and device topologies, novel applications, more demanding mission profiles, etc. In conclusion, it is getting harder to counteract the reliability issue by only guard-banding or over-margined designs, which diminish the benefits of CMOS scaling. To tackle the above challenges, this thesis targets the reliability modeling of the Bias Temperature Instability phenomenon in CMOS digital circuits, while covering the scaling impacts from planar to advanced FinFET process technology nodes. The first key contribution of this thesis is to propagate the BTI modeling from device to processor data-path and local memory level. The purpose is to analyze the impacts of the BTI degradation from the physical device level up to the block level to investigate the severeness of the BTI threat in CMOS digital circuits. This thesis also contributes by proposing fast and still accurate simulation frameworks at various design levels. The last key contribution of this thesis is to provide BTI-aware design guidelines at the device, gate and block level. The purpose is to support the CMOS digital circuit designers by providing design-time guidelines that enhance the lifetime and reliability of digital ICs against the BTI phenomenon.1. Introduction 2. Time-Zero and Time-Dependent Variability 3. Bias Temperature Instability Models 4. Scaling of BTI from Planar FET to Advanced 3-D FinFET Nodes 5. BTI Degradation of Logic Gates with the Trap-based Model 6. Gate-level Comparison of BTI Models 7. BTI Aging on Datapath Logic Blocks from Planar to Advanced FinFET Nodes 8. Conclusions and Future Worknrpages: 212status: publishe

A high performance reconfigurable motion estimation hardware architecture

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and high frame rates, the computational complexity of full search (FS) ME algorithm is prohibitively high, while the PSNR obtained by fast search ME algorithms is low. Therefore, in this paper, we propose a new ME algorithm and a high performance reconfigurable systolic ME hardware architecture for efficiently implementing this algorithm. The proposed ME algorithm performs up to three different granularity search iterations in different size search ranges based on the application requirements. Simulation results showed that the proposed ME algorithm performs very close to FS algorithm, even though it searches much fewer search locations than FS algorithm. It outperforms successful fast search ME algorithms by searching more search locations than these algorithms. The proposed reconfigurable ME hardware is implemented in VHDL and mapped to a low cost Xilinx XC3S1500-5 FPGA. It works at 130 MHz and is capable of processing high definition and high frame rate video formats in real time. Therefore, it can be used in flat panel displays for frame rate conversion and de-interlacing, and in video encoders